From e53161d6b9191533caeea0ef6148f247f4e22441 Mon Sep 17 00:00:00 2001 From: salmonik Date: Sun, 1 Nov 2026 16:55:14 +0100 Subject: ehci: diagnostics + hardening for the port-not-enabled case Second OptiPlex QR: the Host System Error is gone (the 64-bit QH/qTD layout fix worked), but the SETUP qTD now halts with TBYTES=0, C_ERR=3 and no XactErr/Babble/DBE -- a split transaction with no valid response. PORTSC shows CCS=1, PP=1 but PED=0, i.e. the port never enabled, so the split has no TT to address. On Intel PCH a healthy USB2 port shows the rate-matching hub as high-speed (PED=1), so the next step is to see every port's state. - settle 100 ms after powering ports and clear stale change bits before the reset walk (RMHs come up slower than direct devices) - retry the port reset once after settling - log a clear line when a connected port remains disabled - retry a failed full-speed device as low-speed (the PORTSC speed field is only valid once the port is enabled) - persistent bottom-row summary: controller count, caps64, USB legacy handoff result, every connected port's PORTSC and the HID device count. A hardware run without serial now reports the whole picture instead of one QR. --- DEBUG_NOTES.md | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'DEBUG_NOTES.md') diff --git a/DEBUG_NOTES.md b/DEBUG_NOTES.md index cd2b9ae..c9efdc1 100644 --- a/DEBUG_NOTES.md +++ b/DEBUG_NOTES.md @@ -664,3 +664,38 @@ hardware exposed this. tail): HID qTD at QH+0x80; control qTDs at +0x100/+0x140/+0x180 and the setup packet at +0x1C0. The failure QR now prints `c64=` and the DMA bases (async/xfer/setup/buf) so the next run is self-describing. + +### OptiPlex 7010 — second hardware QR (after the 64-bit layout fix) + +``` +EHCI fail stage=1 t=20ms sp=0 dev=0 in=true len=18 c64=1 +cmd=00000021 sts=00008003 +prtsc0=0x00001005 hp=0x00003000 +qh1=48084000 qh2=40800000 nqtd=012081c0 +setup=00080e42 data=80120d80 stat=80008c80 +dma a=01208000 x=01208080 s=01208240 b=0120b000 +``` + +- `sts=0x8003`: USBINT|USBERRINT|ASS — **no HSE**, the 64-bit QH/qTD layout is + fixed and the controller runs. +- `stage=1`: the **SETUP qTD halted**, `setup=0x00080e42` -> TBYTES 0, + Halted, C_ERR still 3, no XactErr/Babble/DBE (a split that got no valid + response). +- `prtsc0=0x1005`: device connected + powered, **PED=0** (port never + enabled), speed field reads full-speed. + +On Intel PCH the USB2 physical ports sit behind the integrated Rate Matching +Hub, so a healthy root port shows the hub as a **high-speed** device +(`PED=1`). PED=0 with a connected device means the port did not enable, and +a full/low-speed split has no valid TT to talk to -> SETUP halts. + +Follow-up hardening in the driver: +- 100 ms power-up settle (RMHs are slow) and stale port-change bits cleared + before the reset walk +- one reset retry after a settle +- explicit log line when a connected port stays disabled +- low-speed retry for a failed full-speed device (the PORTSC speed field is + only trustworthy once the port is enabled) +- persistent bottom-row summary: per controller `64b=`/`leg=` handoff result, + every connected port's PORTSC, and the HID device count — hardware runs + without serial now show the whole picture, not just the first QR -- cgit v1.2.3