1 files changed, 56 insertions, 40 deletions

diff --git a/src/interrupts.rs b/src/interrupts.rs
index 204d3d7..90d5bbb 100644
--- a/src/interrupts.rs
+++ b/src/interrupts.rs
@@ -12,13 +12,13 @@ use core::sync::atomic::{AtomicU16, Ordering};
 #[derive(Copy, Clone)]
 #[repr(C, packed)]
 struct IdtEntry {
-    offset_lo:  u16,
-    selector:   u16,
-    ist:        u8,
-    flags:      u8,
+    offset_lo: u16,
+    selector: u16,
+    ist: u8,
+    flags: u8,
     offset_mid: u16,
-    offset_hi:  u32,
-    _reserved:  u32,
+    offset_hi: u32,
+    _reserved: u32,
 }
 
 /// Fill one IDT entry at the given offset (in bytes).
@@ -27,13 +27,13 @@ unsafe fn idt_set_entry(idt: *mut u8, vec: u8, handler: u64, selector: u16, flag
         let off = (vec as usize) * 16;
         let p = idt.add(off) as *mut IdtEntry;
         p.write(IdtEntry {
-            offset_lo:  handler as u16,
+            offset_lo: handler as u16,
             selector,
-            ist:        0,
-            flags:      flags | 0x80, // bit 7 = present
+            ist: 0,
+            flags: flags | 0x80, // bit 7 = present
             offset_mid: (handler >> 16) as u16,
-            offset_hi:  (handler >> 32) as u32,
-            _reserved:  0,
+            offset_hi: (handler >> 32) as u32,
+            _reserved: 0,
         });
     }
 }
@@ -46,9 +46,9 @@ static mut IDTR: [u16; 5] = [0; 5]; // 2-byte limit + 4-byte base (48-bit pseudo
 // PIC (8259A)
 // ---------------------------------------------------------------------------
 
-const PIC1_CMD:  u16 = 0x20;
+const PIC1_CMD: u16 = 0x20;
 const PIC1_DATA: u16 = 0x21;
-const PIC2_CMD:  u16 = 0xA0;
+const PIC2_CMD: u16 = 0xA0;
 const PIC2_DATA: u16 = 0xA1;
 
 const PIC_EOI: u8 = 0x20;
@@ -89,8 +89,8 @@ fn eoi(irq: u8) {
 // PIT timer (channel 0, ~100 Hz)
 // ---------------------------------------------------------------------------
 
-const PIT_CMD:  u16 = 0x43;
-const PIT_CH0:  u16 = 0x40;
+const PIT_CMD: u16 = 0x43;
+const PIT_CH0: u16 = 0x40;
 const PIT_FREQ: u64 = 1_193_182;
 
 /// Set up PIT channel 0 in mode 2 (rate generator) at `hz` (1–1000ish).
@@ -177,7 +177,9 @@ impl KeyBuf {
         if next.wrapping_sub(h) as u16 > 255 {
             return; // drop — ring is full
         }
-        unsafe { *self.buf[t as usize & 255].get() = byte; }
+        unsafe {
+            *self.buf[t as usize & 255].get() = byte;
+        }
         // Ensure byte is globally visible before incrementing tail.
         self.tail.store(next, Ordering::Release);
     }
@@ -206,8 +208,8 @@ core::arch::global_asm!(
     ".globl isr_stub_32",
     ".p2align 4",
     "isr_stub_32:",
-    "    push 0",          // error code (non-exception)
-    "    push 32",         // vector
+    "    push 0",  // error code (non-exception)
+    "    push 32", // vector
     "    jmp  isr_common",
     "",
     ".globl isr_stub_33",
@@ -243,7 +245,7 @@ core::arch::global_asm!(
     "    push r14",
     "    push r15",
     "",
-    "    mov rdi, rsp",              // first arg: pointer to saved registers
+    "    mov rcx, rsp", // first arg (rcx = MS x64 ABI)
     "    call isr_dispatch",
     "",
     "    pop r15",
@@ -261,36 +263,50 @@ core::arch::global_asm!(
     "    pop rdx",
     "    pop rcx",
     "    pop rax",
-    "    add rsp, 16",               // pop vector + error code
+    "    add rsp, 16", // pop vector + error code
     "    iretq",
 );
 
 /// Saved register frame (as pushed by `isr_common`).
 #[repr(C)]
 struct IntFrame {
-    r15:  u64, r14: u64, r13: u64, r12: u64,
-    r11:  u64, r10: u64, r9:  u64, r8:  u64,
-    rdi:  u64, rsi: u64, rbp: u64, rbx: u64,
-    rdx:  u64, rcx: u64, rax: u64,
-    vector:   u64,
-    error:    u64,
-    rip:      u64,
-    cs:       u64,
-    rflags:   u64,
+    r15: u64,
+    r14: u64,
+    r13: u64,
+    r12: u64,
+    r11: u64,
+    r10: u64,
+    r9: u64,
+    r8: u64,
+    rdi: u64,
+    rsi: u64,
+    rbp: u64,
+    rbx: u64,
+    rdx: u64,
+    rcx: u64,
+    rax: u64,
+    vector: u64,
+    error: u64,
+    rip: u64,
+    cs: u64,
+    rflags: u64,
 }
 
 /// Called from the asm common handler — dispatches to the right Rust handler.
 #[no_mangle]
-extern "C" fn isr_dispatch(frame: &IntFrame) {
-    match frame.vector {
-        32 => timer_irq(),
-        33 => keyboard_irq(),
-        0xFF => { /* spurious — ignore */ }
-        other => {
-            // Log unexpected interrupt on serial (but don't halt — might be benign).
-            crate::serial::write_str("intr: unhandled vector ");
-            crate::serial::put_byte(other as u8);
-            crate::serial::put_byte(b'\n');
+unsafe extern "C" fn isr_dispatch(frame: &IntFrame) {
+    unsafe {
+        match frame.vector {
+            32 => eoi(0),
+            33 => {
+                let byte: u8;
+                core::arch::asm!("in al, dx", out("al") byte, in("dx") 0x60u16,
+                    options(nostack, preserves_flags));
+                // Push scancode to ring buffer (called with interrupts disabled).
+                KEYBUF.push(byte);
+                eoi(1);
+            }
+            _ => {}
         }
     }
 }
@@ -346,7 +362,7 @@ pub fn init() {
 
         // Build the IDTR pseudo-descriptor.
         IDTR = [
-            (256u16 * 16 - 1) as u16,     // limit = 256*16 - 1
+            (256u16 * 16 - 1) as u16,      // limit = 256*16 - 1
             idt_ptr as u16,                // base lo
             (idt_ptr as u64 >> 16) as u16, // base mid
             (idt_ptr as u64 >> 32) as u16, // base hi