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| author | salmonik <salmonik@tuta.io> | 2026-11-01 16:48:40 +0100 |
|---|---|---|
| committer | salmonik <salmonik@tuta.io> | 2026-11-01 16:48:40 +0100 |
| commit | 12549dabf96bd6eb08c6834134fedf9edc7452b5 (patch) | |
| tree | 2237ed1a05b731f0e1a39c2374440cec3c872258 /bins/mem/Cargo.toml | |
| parent | scripts: add test-usb; fix duplicate -bios in the test harness (diff) | |
| download | rs-dos-12549dabf96bd6eb08c6834134fedf9edc7452b5.tar.gz rs-dos-12549dabf96bd6eb08c6834134fedf9edc7452b5.zip | |
ehci: reserve the 64-bit QH/qTD layout (fixes hardware HSE)
First OptiPlex run: the controller halted with HSE (USBSTS bit4) 20 ms into
the first control transfer, with otherwise valid QH/qTD fields (control QH,
DTC, MPS 8, split hub 0/port 1, active qTD).
The PCH EHCI advertises HCCPARAMS bit0 (64-bit addressing capability), which
extends every QH with bufptr_hi[5] (17 dwords / 68 B) and every qTD the same
way (13 dwords / 52 B). Packing them 32-bit-style (48/32 B) made the
controller read the next qTD as the overlay's high buffer pointer and DMA to
a bogus 64-bit address -> Host System Error.
Space every structure for the 64-bit variant (32-bit controllers ignore the
tail): HID qTD at QH+0x80; control qTDs at QH+0x100/0x140/0x180 with the
setup packet at +0x1C0. The failure QR now reports the capability and the
DMA bases so the next hardware iteration is self-describing.
Diffstat (limited to 'bins/mem/Cargo.toml')
0 files changed, 0 insertions, 0 deletions